1. Field of Invention
The present invention relates to a method for manufacturing a well structure for integrated circuits. More particularly, the present invention relates to a method of forming a well in the integrated circuit before the definition of active device areas.
2. Description of Related Art
There are two types of devices in an integrated circuit, namely, a logic device and a memory device. Logic devices are used for carrying out the computation of logic functions, for example, in the microprocessor of a personal computer. On the other hand, memory devices, for example, random access memories (RAMs), are used for storing digital data. As a microprocessor becomes functionally more powerful, software programs that can be executed also can be very large. Hence, the storage capacity of memory must correspondingly be increased.
At present, most semiconductor storage devices, for example, dynamic random access memories (DRAMs) are made from complementary metallic oxide semiconductor (CMOS) transistors. As the level of integration for semiconductors is increased, the use of CMOS transistors is going to be much common. The design of a CMOS involves three types of structural formation, namely: an N-well, a P-well and a twin well. Among the three, N-well and P-well are single well construction. Due to the need for a high level of integration, the dimensions of a device are constantly decreased.
When the feature linewidth of a device has fallen to below 1 .mu.m, because of the short-channel effect, field intensity inside the channel region will be increased. Consequently, the operational characteristics of a P-type MOS transistor and an N-type MOS transistor is approaching each other. Therefore, a more suitable choice for sub-micron technologies will be to use CMOS transistors with a twin well structure.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in forming a conventional twin well structure. First, as shown in FIG. 1A, photolithographic and etching techniques are used to pattern PMOS 11 and NMOS 12 active areas on the &lt;100&gt; surface of a P-type substrate 10, which has a resistivity of about 8 to 12 .OMEGA.-cm. The substrate 10 further includes a pad oxide layer 13, and silicon nitride layers 14 and a patterned photoresist layer 15 for patterning the substrate 10. Next, the photoresist layer 15 is removed.
Then, using a photolithographic process, a photoresist layer 16 is formed over the substrate 10, and patterned to cover only the area 12 where the N-MOS transistor will be placed as shown in FIG. 1B. Next, impurity ions 17, for example, phosphorus ion, for forming the N-type semiconductor are implanted into the exposed substrate 10 as shown in FIG. 1C. Since the energy used for implanting ions to form the N-well is high and the combined thickness of the silicon nitride layer 14 and the pad oxide layer 13 is rather thin (below about 2500 .ANG.), N-type ions will be able to penetrate through these two layers and end up in the substrate. The energy level used in the N-type ion implant is about 200 to 500 KeV and the dosage level is about 1.0.times.10.sup.13 to 3.0.times.10.sup.13 /cm.sup.2.
In a subsequent step, the photoresist layer 16 is removed, and then the wafer is placed in a furnace and then raised to a temperature of about 1000.degree. C. to allow the doped impurities to drive into the substrate through diffusion. The resulting N-well concentration profile 18 is shown in FIG. 1D.
In the aforementioned conventional method, patterning of the active area is carried out prior to performing the implant operation. This is because the pattern on the active area can serve as an alignment layer in the well implant operation. In other words, because the well implantation operation itself cannot generate an alignment mark, no well implantation operation can be carried out before the definition of the active area. However, in order to allow the impurity ions to pass through the silicon nitride/pad oxide layers into the substrate successfully, a higher level of implant energy needs to be supplied.
The problem of high-energy implant is that the impurity ions will cause damages to the substrate surface. In addition, the nitride and oxygen atoms that are bombarded upon will be forced into the substrate surface and further causing additional defects on the substrate layer. Damages or defects in the substrate will lower the charge-to-breakdown (Q.sub.BD) voltage of the subsequently formed gate oxide layer over the substrate, and a low Q.sub.BD lowers the reliability of the integrated circuit device.
In light of the foregoing, there is a need to provide an improved method of manufacturing a twin well structure in an integrated circuit.